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Texas Instruments /MSP432E411Y /EMAC0 /PPSCTRL

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Interpret as PPSCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EMAC_PPSCTRL_PPSCTRL_1HZ)EMAC_PPSCTRL_PPSCTRL 0 (EMAC_PPSCTRL_PPSEN0)EMAC_PPSCTRL_PPSEN0 0 (EMAC_PPSCTRL_TRGMODS0_INTONLY)EMAC_PPSCTRL_TRGMODS0

EMAC_PPSCTRL_TRGMODS0=EMAC_PPSCTRL_TRGMODS0_INTONLY, EMAC_PPSCTRL_PPSCTRL=EMAC_PPSCTRL_PPSCTRL_1HZ

Description

Ethernet MAC PPS Control

Fields

EMAC_PPSCTRL_PPSCTRL

EN0PPS Output Frequency Control (PPSCTRL) or Command Control (PPSCMD)

0 (EMAC_PPSCTRL_PPSCTRL_1HZ): When the PPSEN0 bit = 0x0, the EN0PPS signal is 1 pulse of the PTP reference clock.(of width clk_ptp_i) every second

1 (EMAC_PPSCTRL_PPSCTRL_2HZ): When the PPSEN0 bit = 0x0, the binary rollover is 2 Hz, and the digital rollover is 1 Hz

2 (EMAC_PPSCTRL_PPSCTRL_4HZ): When the PPSEN0 bit = 0x0, the binary rollover is 4 Hz, and the digital rollover is 2 Hz

3 (EMAC_PPSCTRL_PPSCTRL_8HZ): When thePPSEN0 bit = 0x0, the binary rollover is 8 Hz, and the digital rollover is 4 Hz,

4 (EMAC_PPSCTRL_PPSCTRL_16HZ): When thePPSEN0 bit = 0x0, the binary rollover is 16 Hz, and the digital rollover is 8 Hz

5 (EMAC_PPSCTRL_PPSCTRL_32HZ): When thePPSEN0 bit = 0x0, the binary rollover is 32 Hz, and the digital rollover is 16 Hz

6 (EMAC_PPSCTRL_PPSCTRL_64HZ): When thePPSEN0 bit = 0x0, the binary rollover is 64 Hz, and the digital rollover is 32 Hz

7 (EMAC_PPSCTRL_PPSCTRL_128HZ): When thePPSEN0 bit = 0x0, the binary rollover is 128 Hz, and the digital rollover is 64 Hz

8 (EMAC_PPSCTRL_PPSCTRL_256HZ): When thePPSEN0 bit = 0x0, the binary rollover is 256 Hz, and the digital rollover is 128 Hz

9 (EMAC_PPSCTRL_PPSCTRL_512HZ): When thePPSEN0 bit = 0x0, the binary rollover is 512 Hz, and the digital rollover is 256 Hz

10 (EMAC_PPSCTRL_PPSCTRL_1024HZ): When the PPSEN0 bit = 0x0, the binary rollover is 1.024 kHz, and the digital rollover is 512 Hz

11 (EMAC_PPSCTRL_PPSCTRL_2048HZ): When thePPSEN0 bit = 0x0, the binary rollover is 2.048 kHz, and the digital rollover is 1.024 kHz

12 (EMAC_PPSCTRL_PPSCTRL_4096HZ): When thePPSEN0 bit = 0x0, the binary rollover is 4.096 kHz, and the digital rollover is 2.048 kHz

13 (EMAC_PPSCTRL_PPSCTRL_8192HZ): When thePPSEN0 bit = 0x0, the binary rollover is 8.192 kHz, and the digital rollover is 4.096 kHz

14 (EMAC_PPSCTRL_PPSCTRL_16384HZ): When thePPSEN0 bit = 0x0, the binary rollover is 16.384 kHz, and the digital rollover is 8.092 kHz

15 (EMAC_PPSCTRL_PPSCTRL_32768HZ): When thePPSEN0 bit = 0x0, the binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz
EMAC_PPSCTRL_PPSEN0

Flexible PPS Output Mode Enable
EMAC_PPSCTRL_TRGMODS0

Target Time Register Mode for PPS0 Output

0 (EMAC_PPSCTRL_TRGMODS0_INTONLY): Indicates that the Target Time registers are programmed only for generating the interrupt event

2 (EMAC_PPSCTRL_TRGMODS0_INTPPS0): Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the EN0PPS output signal

3 (EMAC_PPSCTRL_TRGMODS0_PPS0ONLY): Indicates that the Target Time registers are programmed only for starting or stopping the generation of the EN0PPS output signal. No interrupt is asserted

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Register License

Software License Agreement

Texas Instruments (TI) is supplying this software for use solely and exclusively on TI’s microcontroller products. The software is owned by TI and/or its suppliers, and is protected under applicable copyright laws. You may not combine this software with “viral” open-source software in order to form a larger program.

THIS SOFTWARE IS PROVIDED “AS IS” AND WITH ALL FAULTS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data